The present invention relates to the architectural design of execution units for data processors and more particularly, to the design of a high speed performance invarient execution unit for non-communicative instructions. The designers of high speed computers are frequently confronted with the task of optimizing the overall performance of arithmetic processors by minimizing the execution time of an instruction, the execution time being the product of the number of steps involved and the cycle time of the processors.
A common approach to the design of an efficient arithmetic processor is to partition the execution into several units each performing a unique task. This approach speeds up the individual units and reduces hardware overhead. Instructions are executed as algorithms with the results of each step being collected from one or more execution unit(s).
In operation an architecture having parallel execution units would begin by reading operands from input buffer storage or the like and then properly multiplexing the operands into the selected execution unit(s) for execution. Following execution, the result would be bussed from the execution unit(s) and written into a buffer storage.
The inefficiencies of such an architecture is apparent since while the operands are being fetched and multiplexed, the execution units are idle. Furthermore, the read time is adversely affected by the presence of "reverse" instructions. A reverse instruction, is denoted by an apostrophe symbol over the instruction symbol. For example, the reverse instruction A-'B is in result the same as the "forward" or normal instruction B - A. To efficiently execute reverse instructions the read address of both operands ("A" and "B" in the example above) must be interchanged thereby increasing cycle time further.